The present subject matter relates to an apparatus and a method for transmitting/receiving signals at high speed, and more particularly, to an apparatus and a method for transmitting/receiving signals and data within a semiconductor memory device and a system having the semiconductor memory device.
In a system implemented with a variety of semiconductor devices, a semiconductor memory device serves as a data storage. When a central processing unit (CPU) requests data, the semiconductor memory device outputs data corresponding to addresses received from the CPU. In addition, the semiconductor memory device stores data received from the CPU into corresponding unit cells.
As the operating speed of the system increases and semiconductor integrated circuit (IC) technologies are rapidly developed, the semiconductor memory devices are required to output or store data at higher speed. In order for the semiconductor memory device to stably operate at higher speed, internal circuits of the semiconductor memory device must be able to operate at a high speed and transmit signals and data therebetween at the high speed.
The semiconductor memory device includes control circuits, signal lines, and transfer circuits. The control circuits read data from unit cells or write data on unit cells through the signal lines. Since data transfer units are provided to transfer data to locations all around the semiconductor memory device having a plurality of banks, their signal lines are longer than any other data transfer unit or other control signal line. In addition, the semiconductor memory device may further include various data transfer units, signal lines, or various circuits so as to obtain its stable operation and prevent interference. However, there is a limitation in high-speed data transmission because such data transfer units have a large load.
As transfer speeds of data/signal buses and lines increase, operating speed of the semiconductor memory device is increasing. Especially, operation performance of the semiconductor memory device is improved when the semiconductor memory device outputs data stored in unit cells at a high speed after an external command is inputted. Regarding this, a column address strobe (CAS) latency is described in the specification of the semiconductor memory device. The CAS latency represents number of clocks from an input of an external read command to an output of data stored in a unit cell. As data is outputted at higher speed after the input of the external read command, the operating speed of the semiconductor memory device increases and its operation performance improves.
When the external read command is inputted, the semiconductor memory device recognizes a unit cell corresponding to an inputted address. At this point, a predetermined delay time occurs during the process of selecting the unit cell. Then, data stored in the selected unit cell is transferred through a data transfer unit to an output driver. Finally, the data is outputted through an output buffer to an external circuit. The process of transferring the data through the data transfer unit spends a significant portion of time necessary for outputting the data after the input of the read command. The reduction of this time can greatly contribute to increasing the operating speed of the semiconductor memory device.
FIG. 1 is a block diagram of a conventional semiconductor memory device.
Referring to FIG. 1, the conventional semiconductor memory device includes a timing controller 110, a main driver 120, a data transferrer 130, and a receiver 140.
The timing controller 110 receives an enable signal EN to output a control signal DRVON for controlling the main driver 120. The enable signal EN enables circuits for transmitting/receiving data DATA according to an input of an external read command during a data output operation. The timing controller 110 enables the main driver 120 for a predetermined time necessary for transmitting the input data DATA by delaying the enable signal EN. The timing controller 110 can reduce unnecessary power consumption by enabling the main driver 120 only for a necessary time.
The main driver 120 transfers the input data DATA to the data transferrer 130 under the control of the timing controller 110. The data transferred through the data transferrer 130 is recognized by the receiver 140, and the recognized data is outputted through an output buffer (not shown) to an external circuit (not shown). In this way, the external circuit can acquire the output data OUT corresponding to the external command.
The data transferrer 130 is connected to a plurality of regions within the semiconductor memory devices, e.g., banks each having a plurality of unit cells. Accordingly, the main driver 120 transfers logic low data or logic high data, or interrupts the data transmission to the data transferrer 130 when no valid data exists.
FIGS. 2A and 2B are circuit diagrams of the main driver 120 and the receiver 140, respectively.
Referring to FIG. 2A, the main driver 120 includes a tri-state driver configured to output the input data DATA in response to the control signal DRVON. The main driver 120 outputs a signal corresponding to an inverted level of the input data DATA to the data transferrer 130 during an activation of the control signal DRVON. The internal structure and operation of the main driver 120 implemented with a plurality of logic gates and transistors are well known to those skilled in the art and thus their detailed description will be omitted.
Because the main driver of FIG. 2A outputs the signal having the inverted level of the input data DATA, the receiver 140 of FIG. 1 is implemented with a single inverter, as illustrated in FIG. 2B.
The conventional semiconductor memory device transmits/receives data using the circuits of FIGS. 1, 2A and 2B. That is, the main driver 120 transmits the data under the control of the timing controller 110. However, when the data transferrer 130 has a large load, the data transfer speed in the data transferrer 130 reduces and the data transfer time increases.
In particular, when the data transferrer 130 is shared by a plurality of banks, unexpected delay may occur during the data transfer operation due to RC parameters, that is, resistance and parasitic capacitance of the data transferrer 130. Therefore, the signal or data transfer speed needs to increase in the delay region such as the data transferrer with a large load.